In addition to complex device structures, integrated circuits generally comprise conductive elements separated by insulating elements. Such constructions essentially form parallel plate capacitors. Parallel plate capacitance can be described by the well-known equation:
                              C          =                                    k              ⁢                                                          ⁢                              ɛ                0                            ⁢              A                        d                          ,                            (        1        )            wherein C is capacitance, k is the dielectric coefficient of the material between the plates, ∈0 is the permittivity of free space, A is the plate area and d is the distance between plates. As feature size continues to decrease and packing density continues to increase, dielectric layers that separate conductive elements, particularly metal layers, become thinner, thus decreasing d in the equation above. As d decreases, capacitance increases.
Pin capacitance is a measure of overall parasitic capacitance within a chip as measured across particular pins in a fully fabricated and packaged integrated circuit. It is desirable to make pin capacitance as low as possible, as an increased level can slow down the transfer of signals to and from the devices on the chip and can increase the power needed to drive the pins. In addition, bus speeds are becoming faster, into the GHz range. To accommodate these higher speeds, pin capacitance requirements, as specified by manufacturers such as Intel Corp., are being reduced and are better matched between pins.
Thus, a need exists to reduce parasitic capacitance in order to make full use of the faster speeds at which current devices can operate and to reduce the power required to drive them.